UVD_CGC_STATUS__MPC_DCLK__SHIFT  165 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x00000014
UVD_CGC_STATUS__MPC_DCLK__SHIFT  204 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
UVD_CGC_STATUS__MPC_DCLK__SHIFT  220 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
UVD_CGC_STATUS__MPC_DCLK__SHIFT  222 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
UVD_CGC_STATUS__MPC_DCLK__SHIFT  866 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14
UVD_CGC_STATUS__MPC_DCLK__SHIFT 1886 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14
UVD_CGC_STATUS__MPC_DCLK__SHIFT 1936 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14