UVD_CGC_STATUS__MPC_DCLK_MASK  164 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
UVD_CGC_STATUS__MPC_DCLK_MASK  203 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
UVD_CGC_STATUS__MPC_DCLK_MASK  219 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
UVD_CGC_STATUS__MPC_DCLK_MASK  221 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
UVD_CGC_STATUS__MPC_DCLK_MASK  898 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L
UVD_CGC_STATUS__MPC_DCLK_MASK 1917 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L
UVD_CGC_STATUS__MPC_DCLK_MASK 1967 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L