UVD_CGC_STATUS__LRBBM_SCLK__SHIFT  163 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x00000017
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT  210 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT  226 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT  228 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT  869 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 1889 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17
UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 1939 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17