UVD_CGC_STATUS__LRBBM_SCLK_MASK  162 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
UVD_CGC_STATUS__LRBBM_SCLK_MASK  209 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
UVD_CGC_STATUS__LRBBM_SCLK_MASK  225 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
UVD_CGC_STATUS__LRBBM_SCLK_MASK  227 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
UVD_CGC_STATUS__LRBBM_SCLK_MASK  901 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L
UVD_CGC_STATUS__LRBBM_SCLK_MASK 1920 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L
UVD_CGC_STATUS__LRBBM_SCLK_MASK 1970 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L