UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT  161 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0x0000000d
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT  190 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT  206 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT  208 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT  859 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 1879 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd
UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 1929 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd