UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT  159 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0x0000000c
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT  188 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT  204 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT  206 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT  858 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 1878 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc
UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 1928 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc