UVD_CGC_STATUS__LMI_MC_SCLK_MASK  158 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
UVD_CGC_STATUS__LMI_MC_SCLK_MASK  187 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
UVD_CGC_STATUS__LMI_MC_SCLK_MASK  203 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
UVD_CGC_STATUS__LMI_MC_SCLK_MASK  205 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
UVD_CGC_STATUS__LMI_MC_SCLK_MASK  890 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L
UVD_CGC_STATUS__LMI_MC_SCLK_MASK 1909 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L
UVD_CGC_STATUS__LMI_MC_SCLK_MASK 1959 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L