UVD_CGC_STATUS__IDCT_VCLK__SHIFT  153 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0x0000000f
UVD_CGC_STATUS__IDCT_VCLK__SHIFT  194 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
UVD_CGC_STATUS__IDCT_VCLK__SHIFT  210 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
UVD_CGC_STATUS__IDCT_VCLK__SHIFT  212 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
UVD_CGC_STATUS__IDCT_VCLK__SHIFT  861 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf
UVD_CGC_STATUS__IDCT_VCLK__SHIFT 1881 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf
UVD_CGC_STATUS__IDCT_VCLK__SHIFT 1931 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf