UVD_CGC_STATUS__IDCT_SCLK__SHIFT  151 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0x0000000e
UVD_CGC_STATUS__IDCT_SCLK__SHIFT  192 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
UVD_CGC_STATUS__IDCT_SCLK__SHIFT  208 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
UVD_CGC_STATUS__IDCT_SCLK__SHIFT  210 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
UVD_CGC_STATUS__IDCT_SCLK__SHIFT  860 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe
UVD_CGC_STATUS__IDCT_SCLK__SHIFT 1880 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe
UVD_CGC_STATUS__IDCT_SCLK__SHIFT 1930 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe