UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK  138 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L
UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK  699 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK  869 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK  859 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80