UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 137 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x00000005 UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 696 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 866 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 856 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5