UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK  136 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L
UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK  695 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK  865 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK  855 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20