UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK  128 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L
UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK  687 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK  857 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK  847 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2