UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK  126 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L
UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK  709 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK  879 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK  869 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000