UVD_CGC_GATE__IDCT__SHIFT   79 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT 0x00000007
UVD_CGC_GATE__IDCT__SHIFT  138 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT 0x7
UVD_CGC_GATE__IDCT__SHIFT  150 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT 0x7
UVD_CGC_GATE__IDCT__SHIFT  152 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT 0x7
UVD_CGC_GATE__IDCT__SHIFT  384 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
UVD_CGC_GATE__IDCT__SHIFT  812 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
UVD_CGC_GATE__IDCT__SHIFT 1830 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
UVD_CGC_GATE__IDCT__SHIFT 1882 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7