UVD_CGC_CTRL__WCB_MODE_MASK   76 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
UVD_CGC_CTRL__WCB_MODE_MASK  261 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
UVD_CGC_CTRL__WCB_MODE_MASK  283 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
UVD_CGC_CTRL__WCB_MODE_MASK  285 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
UVD_CGC_CTRL__WCB_MODE_MASK  461 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
UVD_CGC_CTRL__WCB_MODE_MASK  954 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
UVD_CGC_CTRL__WCB_MODE_MASK 1973 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
UVD_CGC_CTRL__WCB_MODE_MASK 2022 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L