UVD_CGC_CTRL__UDEC_MP_MODE_MASK   70 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
UVD_CGC_CTRL__UDEC_MP_MODE_MASK  235 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
UVD_CGC_CTRL__UDEC_MP_MODE_MASK  257 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
UVD_CGC_CTRL__UDEC_MP_MODE_MASK  259 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
UVD_CGC_CTRL__UDEC_MP_MODE_MASK  448 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
UVD_CGC_CTRL__UDEC_MP_MODE_MASK  941 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
UVD_CGC_CTRL__UDEC_MP_MODE_MASK 1960 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
UVD_CGC_CTRL__UDEC_MP_MODE_MASK 2009 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L