UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 67 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0x0000000d UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 232 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 254 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 256 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 423 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 916 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 1934 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 1984 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd