UVD_CGC_CTRL__UDEC_IT_MODE_MASK 66 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L UVD_CGC_CTRL__UDEC_IT_MODE_MASK 231 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 UVD_CGC_CTRL__UDEC_IT_MODE_MASK 253 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 UVD_CGC_CTRL__UDEC_IT_MODE_MASK 255 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 UVD_CGC_CTRL__UDEC_IT_MODE_MASK 446 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L UVD_CGC_CTRL__UDEC_IT_MODE_MASK 939 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L UVD_CGC_CTRL__UDEC_IT_MODE_MASK 1958 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L UVD_CGC_CTRL__UDEC_IT_MODE_MASK 2007 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L