UVD_CGC_CTRL__UDEC_DB_MODE_MASK   64 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
UVD_CGC_CTRL__UDEC_DB_MODE_MASK  233 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
UVD_CGC_CTRL__UDEC_DB_MODE_MASK  255 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
UVD_CGC_CTRL__UDEC_DB_MODE_MASK  257 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
UVD_CGC_CTRL__UDEC_DB_MODE_MASK  447 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
UVD_CGC_CTRL__UDEC_DB_MODE_MASK  940 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
UVD_CGC_CTRL__UDEC_DB_MODE_MASK 1959 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
UVD_CGC_CTRL__UDEC_DB_MODE_MASK 2008 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L