UVD_CGC_CTRL__UDEC_CM_MODE_MASK   62 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
UVD_CGC_CTRL__UDEC_CM_MODE_MASK  229 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
UVD_CGC_CTRL__UDEC_CM_MODE_MASK  251 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
UVD_CGC_CTRL__UDEC_CM_MODE_MASK  253 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
UVD_CGC_CTRL__UDEC_CM_MODE_MASK  445 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
UVD_CGC_CTRL__UDEC_CM_MODE_MASK  938 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
UVD_CGC_CTRL__UDEC_CM_MODE_MASK 1957 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
UVD_CGC_CTRL__UDEC_CM_MODE_MASK 2006 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L