UVD_CGC_CTRL__REGS_MODE_MASK 56 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L UVD_CGC_CTRL__REGS_MODE_MASK 243 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 UVD_CGC_CTRL__REGS_MODE_MASK 265 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 UVD_CGC_CTRL__REGS_MODE_MASK 267 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 UVD_CGC_CTRL__REGS_MODE_MASK 452 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L UVD_CGC_CTRL__REGS_MODE_MASK 945 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L UVD_CGC_CTRL__REGS_MODE_MASK 1964 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L UVD_CGC_CTRL__REGS_MODE_MASK 2013 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L