UVD_CGC_CTRL__MPC_MODE_MASK   48 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
UVD_CGC_CTRL__MPC_MODE_MASK  255 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_4_2_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
UVD_CGC_CTRL__MPC_MODE_MASK  277 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
UVD_CGC_CTRL__MPC_MODE_MASK  279 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_6_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
UVD_CGC_CTRL__MPC_MODE_MASK  458 drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
UVD_CGC_CTRL__MPC_MODE_MASK  951 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
UVD_CGC_CTRL__MPC_MODE_MASK 1970 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
UVD_CGC_CTRL__MPC_MODE_MASK 2019 drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h #define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L