BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 17944 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 34673 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h #define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8