UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 12034 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 11846 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 9278 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 4480 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0