UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 11995 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 11807 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40
UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 9223 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L
UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 4439 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40