UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 11990 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 11802 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2
UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 9216 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002
UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 4434 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2