UMC_BASE__INST5_SEG3 1463 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST5_SEG3                       0
UMC_BASE__INST5_SEG3  809 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST5_SEG3                       0
UMC_BASE__INST5_SEG3 1026 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST5_SEG3                       0
UMC_BASE__INST5_SEG3 1026 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST5_SEG3                       0
UMC_BASE__INST5_SEG3 1271 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST5_SEG3                       0
UMC_BASE__INST5_SEG3  878 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST5_SEG3                       0