UMC_BASE__INST5_SEG2 1462 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST5_SEG2                       0x00426C00
UMC_BASE__INST5_SEG2  808 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST5_SEG2                       0
UMC_BASE__INST5_SEG2 1025 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST5_SEG2                       0
UMC_BASE__INST5_SEG2 1025 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST5_SEG2                       0
UMC_BASE__INST5_SEG2 1270 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST5_SEG2                       0
UMC_BASE__INST5_SEG2  877 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST5_SEG2                       0