UMC_BASE__INST5_SEG1 1461 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST5_SEG1 0x00154000 UMC_BASE__INST5_SEG1 807 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST5_SEG1 0 UMC_BASE__INST5_SEG1 1024 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST5_SEG1 0 UMC_BASE__INST5_SEG1 1024 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST5_SEG1 0 UMC_BASE__INST5_SEG1 1269 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST5_SEG1 0 UMC_BASE__INST5_SEG1 876 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST5_SEG1 0