UMC_BASE__INST5_SEG0 1460 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST5_SEG0 0x00013360 UMC_BASE__INST5_SEG0 806 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST5_SEG0 0 UMC_BASE__INST5_SEG0 1023 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST5_SEG0 0 UMC_BASE__INST5_SEG0 1023 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST5_SEG0 0 UMC_BASE__INST5_SEG0 1268 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST5_SEG0 0 UMC_BASE__INST5_SEG0 875 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST5_SEG0 0