UMC_BASE__INST4_SEG2 1455 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST4_SEG2 0x00426800 UMC_BASE__INST4_SEG2 801 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST4_SEG2 0 UMC_BASE__INST4_SEG2 1019 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST4_SEG2 0 UMC_BASE__INST4_SEG2 1019 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST4_SEG2 0 UMC_BASE__INST4_SEG2 1264 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST4_SEG2 0 UMC_BASE__INST4_SEG2 1111 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST4_SEG2 0 UMC_BASE__INST4_SEG2 870 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST4_SEG2 0