UMC_BASE__INST4_SEG1 1454 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST4_SEG1 0x00114000 UMC_BASE__INST4_SEG1 800 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST4_SEG1 0 UMC_BASE__INST4_SEG1 1018 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST4_SEG1 0 UMC_BASE__INST4_SEG1 1018 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST4_SEG1 0 UMC_BASE__INST4_SEG1 1263 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST4_SEG1 0 UMC_BASE__INST4_SEG1 1110 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST4_SEG1 0 UMC_BASE__INST4_SEG1 869 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST4_SEG1 0