UMC_BASE__INST4_SEG0 1453 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST4_SEG0 0x00013340 UMC_BASE__INST4_SEG0 799 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST4_SEG0 0 UMC_BASE__INST4_SEG0 1017 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST4_SEG0 0 UMC_BASE__INST4_SEG0 1017 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST4_SEG0 0 UMC_BASE__INST4_SEG0 1262 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST4_SEG0 0 UMC_BASE__INST4_SEG0 1109 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST4_SEG0 0 UMC_BASE__INST4_SEG0 868 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST4_SEG0 0