UMC_BASE__INST3_SEG2 1448 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST3_SEG2                       0x00426400
UMC_BASE__INST3_SEG2  794 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST3_SEG2                       0
UMC_BASE__INST3_SEG2 1013 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST3_SEG2                       0
UMC_BASE__INST3_SEG2 1013 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST3_SEG2                       0
UMC_BASE__INST3_SEG2 1258 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST3_SEG2                       0
UMC_BASE__INST3_SEG2 1105 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST3_SEG2                      0
UMC_BASE__INST3_SEG2  863 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST3_SEG2                       0