UMC_BASE__INST3_SEG1 1447 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST3_SEG1                       0x000D4000
UMC_BASE__INST3_SEG1  793 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST3_SEG1                       0
UMC_BASE__INST3_SEG1 1012 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST3_SEG1                       0x02426400
UMC_BASE__INST3_SEG1 1012 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST3_SEG1                       0x02426400
UMC_BASE__INST3_SEG1 1257 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST3_SEG1                       0
UMC_BASE__INST3_SEG1 1104 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST3_SEG1                      0
UMC_BASE__INST3_SEG1  862 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST3_SEG1                       0