UMC_BASE__INST3_SEG0 1446 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST3_SEG0                       0x00013320
UMC_BASE__INST3_SEG0  792 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST3_SEG0                       0
UMC_BASE__INST3_SEG0 1011 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST3_SEG0                       0x000D4000
UMC_BASE__INST3_SEG0 1011 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST3_SEG0                       0x000D4000
UMC_BASE__INST3_SEG0 1256 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST3_SEG0                       0
UMC_BASE__INST3_SEG0 1103 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST3_SEG0                      0
UMC_BASE__INST3_SEG0  861 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST3_SEG0                       0