UMC_BASE__INST2_SEG1 1440 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST2_SEG1                       0x00094000
UMC_BASE__INST2_SEG1  786 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST2_SEG1                       0
UMC_BASE__INST2_SEG1 1006 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST2_SEG1                       0x02426000
UMC_BASE__INST2_SEG1 1006 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST2_SEG1                       0x02426000
UMC_BASE__INST2_SEG1 1251 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST2_SEG1                       0
UMC_BASE__INST2_SEG1 1098 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST2_SEG1                      0
UMC_BASE__INST2_SEG1  855 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST2_SEG1                       0