UMC_BASE__INST2_SEG0 1439 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST2_SEG0 0x00013300 UMC_BASE__INST2_SEG0 785 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST2_SEG0 0 UMC_BASE__INST2_SEG0 1005 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST2_SEG0 0x00094000 UMC_BASE__INST2_SEG0 1005 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST2_SEG0 0x00094000 UMC_BASE__INST2_SEG0 1250 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST2_SEG0 0 UMC_BASE__INST2_SEG0 1097 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST2_SEG0 0 UMC_BASE__INST2_SEG0 854 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST2_SEG0 0