UMC_BASE__INST1_SEG4 1436 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST1_SEG4                       0
UMC_BASE__INST1_SEG4  782 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST1_SEG4                       0
UMC_BASE__INST1_SEG4 1003 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST1_SEG4                       0
UMC_BASE__INST1_SEG4 1003 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST1_SEG4                       0
UMC_BASE__INST1_SEG4 1248 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST1_SEG4                       0
UMC_BASE__INST1_SEG4 1095 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST1_SEG4                      0
UMC_BASE__INST1_SEG4  851 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST1_SEG4                       0