UMC_BASE__INST1_SEG3 1435 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST1_SEG3                       0
UMC_BASE__INST1_SEG3  781 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST1_SEG3                       0
UMC_BASE__INST1_SEG3 1002 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST1_SEG3                       0
UMC_BASE__INST1_SEG3 1002 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST1_SEG3                       0
UMC_BASE__INST1_SEG3 1247 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST1_SEG3                       0
UMC_BASE__INST1_SEG3 1094 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST1_SEG3                      0
UMC_BASE__INST1_SEG3  850 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST1_SEG3                       0