UMC_BASE__INST1_SEG2 1434 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST1_SEG2                       0x00425C00
UMC_BASE__INST1_SEG2  780 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST1_SEG2                       0
UMC_BASE__INST1_SEG2 1001 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST1_SEG2                       0
UMC_BASE__INST1_SEG2 1001 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST1_SEG2                       0
UMC_BASE__INST1_SEG2 1246 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST1_SEG2                       0
UMC_BASE__INST1_SEG2 1093 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST1_SEG2                      0
UMC_BASE__INST1_SEG2  849 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST1_SEG2                       0