UMC_BASE__INST1_SEG1 1433 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST1_SEG1                       0x00054000
UMC_BASE__INST1_SEG1  779 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST1_SEG1                       0
UMC_BASE__INST1_SEG1 1000 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST1_SEG1                       0x02425C00
UMC_BASE__INST1_SEG1 1000 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST1_SEG1                       0x02425C00
UMC_BASE__INST1_SEG1 1245 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST1_SEG1                       0x02425C00
UMC_BASE__INST1_SEG1 1092 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST1_SEG1                      0
UMC_BASE__INST1_SEG1  848 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST1_SEG1                       0