UMC_BASE__INST1_SEG0 1432 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST1_SEG0 0x000132E0 UMC_BASE__INST1_SEG0 778 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST1_SEG0 0 UMC_BASE__INST1_SEG0 999 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST1_SEG0 0x00054000 UMC_BASE__INST1_SEG0 999 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST1_SEG0 0x00054000 UMC_BASE__INST1_SEG0 1244 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST1_SEG0 0x00054000 UMC_BASE__INST1_SEG0 1091 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST1_SEG0 0 UMC_BASE__INST1_SEG0 847 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST1_SEG0 0