UMC_BASE__INST0_SEG1 1426 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST0_SEG1                       0x00014000
UMC_BASE__INST0_SEG1  772 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST0_SEG1                       0
UMC_BASE__INST0_SEG1  994 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST0_SEG1                       0x02425800
UMC_BASE__INST0_SEG1  994 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST0_SEG1                       0x02425800
UMC_BASE__INST0_SEG1 1239 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST0_SEG1                       0x02425800
UMC_BASE__INST0_SEG1 1086 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST0_SEG1                      0
UMC_BASE__INST0_SEG1  841 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST0_SEG1                       0