UMC_BASE__INST0_SEG0 1425 drivers/gpu/drm/amd/include/arct_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x000132C0
UMC_BASE__INST0_SEG0  771 drivers/gpu/drm/amd/include/navi10_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x00014000
UMC_BASE__INST0_SEG0  993 drivers/gpu/drm/amd/include/navi12_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x00014000
UMC_BASE__INST0_SEG0  993 drivers/gpu/drm/amd/include/navi14_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x00014000
UMC_BASE__INST0_SEG0 1238 drivers/gpu/drm/amd/include/renoir_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x00014000
UMC_BASE__INST0_SEG0 1085 drivers/gpu/drm/amd/include/vega10_ip_offset.h #define UMC_BASE__INST0_SEG0                      0x00014000
UMC_BASE__INST0_SEG0  840 drivers/gpu/drm/amd/include/vega20_ip_offset.h #define UMC_BASE__INST0_SEG0                       0x00014000