TXQ_CTRL_TXF_BURST_NUM_SHIFT  421 drivers/net/ethernet/atheros/atl1e/atl1e_hw.h #define     TXQ_CTRL_TXF_BURST_NUM_SHIFT    16    /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
TXQ_CTRL_TXF_BURST_NUM_SHIFT  144 drivers/net/ethernet/atheros/atlx/atl1.h #define TXQ_CTRL_TXF_BURST_NUM_SHIFT		16