THM_TMON0_RDIR5_DATA__VALID__SHIFT  485 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0x0000000b
THM_TMON0_RDIR5_DATA__VALID__SHIFT 4300 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT 4290 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT 3508 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT 4422 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT 4120 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT  313 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT                                                                    0xb
THM_TMON0_RDIR5_DATA__VALID__SHIFT  457 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h #define THM_TMON0_RDIR5_DATA__VALID__SHIFT                                                                    0xb