THM_TMON0_RDIR10_DATA__VALID__SHIFT 425 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0x0000000b THM_TMON0_RDIR10_DATA__VALID__SHIFT 4330 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 4320 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 3538 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 4452 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 4150 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 348 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb THM_TMON0_RDIR10_DATA__VALID__SHIFT 492 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb