THM_TMON0_RDIL8_DATA__VALID__SHIFT  407 drivers/gpu/drm/amd/include/asic_reg/smu/smu_6_0_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0x0000000b
THM_TMON0_RDIL8_DATA__VALID__SHIFT 4222 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT 4212 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT 3430 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT 4344 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT 4042 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT  222 drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT                                                                    0xb
THM_TMON0_RDIL8_DATA__VALID__SHIFT  366 drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h #define THM_TMON0_RDIL8_DATA__VALID__SHIFT                                                                    0xb